Method of fabricating a split-gate flash memory

ABSTRACT

A split-gate flash memory is formed by a method described in the following steps. A tunnelling oxide layer, a first conductive layer, and a hard mask layer are formed on a substrate in sequence. A drain opening and a floating gate opening are formed on the hard mask layer by defining the hard mask layer in order to expose the first conductive layer. A first polyoxide layer and a second polyoxide layer are formed on the first conductive layer exposed by the drain opening and the floating gate opening, respectively. The first polyoxide layer and the first conductive layer beneath the first polyoxide layer are removed to expose the substrate in the drain opening. A drain region is formed in the substrate in the drain opening. The hard mask layer is removed, and the first conductive layer is etched into a floating gate using the second polyoxide layer as a mask. A split-gate oxide layer and a second conductive layer are formed on the resulting structure in sequence. A control gate is formed by defining the second conductive layer, and a source region beside the floating gate is formed in the substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application ser.no. 88119924, filed Nov. 16, 1999.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method for fabricating a flash memory, andmore particularly, to a method for fabricating a split-gate flashmemory.

2. Description of the Related Art

At present, nonvolatile memory is widely used in the whole range ofelectrical devices. In particular, programmable nonvolatile memoryhaving a flash memory structure such as the erasable programmableread-only memory and electrically erased programmable read-only memoryhas attracted immense interest. In general, a flash memory comprises twogates, a floating gate for charge storage and a control gate for dataaccessing. The floating gate is in a floating state without beingconnected to any electrical circuit and is located between the controlgate and a substrate while the control gate is connected to a word line.

FIG. 1 is a schematic, cross-sectional view showing a structure of asplit-gate flash memory according to the prior art. In the FIG. 1, afloating gate 102 and a control gate 104 are formed on a substrate 100.A split-gate oxide layer 106 and a dielectric layer 108 separate thefloating gate 102 and the control gate 104. Source/drain regions 110 a,110 b are respectively formed in the substrate 100 adjacent to thecollective structure of the control gate 104 and the floating gate 102.Sometimes, the control gate 104 is referred to as a selective gate.Referring to FIG. 1, the semiconductor process is first to form thefloating gate 102 on the substrate 100 and then to form the split-gateoxide layer 106. Subsequently, a conductive layer is formed on thesplit-gate oxide layer 106. Then, the conductive layer is defined intothe control gate 104 as shown in FIG. 1 by photolithography and etching.Afterwards, an ion implantation process is performed to form thesource/drain regions 110 a, 110 b. A distance L₁ covered by the controlgate 104 between the source/drain region 110 a and the structurecomprising the dielectric layer 108 and the floating gate 102 isreferred to as a channel length of the selective gate.

According to the prior art, the process is first to form the controlgate 104 and then to form the source/drain region 110 a; thus, thechannel length L₁ of the selective gate depends on the accuracy ofphotolithography for defining the control gate 104. Thus, when thephotomask used for defining the control gate 104 is misaligned and thecontrol gate 104 formed is shifted from a desired position, the channellength L₁ is increased or decreased, and the reading current and theprogramming current are varied with the length L₁. When the length L₁ isincreased, the reading current is reduced; thus, a sensitive senseamplifier is required for detecting the reading current. In addition,the programming current is also reduced while the length L₁ isincreased; thus, the time for programming is increased, the speedbecomes slower, and the operation time is increased.

SUMMARY OF THE INVENTION

According to above, the invention provides a method for fabricating asplit-gate flash memory. According to the invention, a drain region anda floating gate are formed before a selective gate is formed in order tofix the distance between the drain region and the floating gate and todecide a channel length thereby. Thus, the invention can stably providea reading current and a programming current and enhance the reliabilityof a device.

The invention provides a method for fabricating a split-gate flashmemory. The method comprises the following steps.

A tunnelling oxide layer, a first conductive layer, and a hard masklayer are formed on a substrate in sequence. A drain opening and afloating gate opening are formed on the hard mask layer by defining thehard mask layer in order to expose the first conductive layer. A firstpolyoxide layer and a second polyoxide layer are formed on the firstconductive layer exposed by the drain opening and the floating gateopening, respectively. The first polyoxide layer and the firstconductive layer beneath the first polyoxide layer are removed to exposethe substrate in the drain opening. A drain is formed in the substratein the drain opening. The hard mask layer is removed, and the firstconductive layer is etched into a floating gate using the secondpolyoxide layer as a mask. A split-gate oxide layer and a secondconductive layer are formed on the resulting structure in sequence. Acontrol gate is formed by defining the second conductive layer, and asource region beside the floating gate is formed in the substrate.

The invention provides another option for the method of fabricating asplit-gate flash memory. The option comprises the following steps.

A tunnelling oxide layer, a first conductive layer, and a hard masklayer are formed on a substrate in sequence. A drain opening and afloating gate opening are formed on the hard mask layer by defining thehard mask layer in order to expose the first conductive layer. The firstconductive layer exposed in the drain opening is removed to expose thesubstrate. A drain is formed in the substrate exposed by the drainopening, and an oxide layer is formed on the drain region. A polyoxidelayer is formed on the first conductive layer exposed by the floatinggate opening. The hard mask layer is removed, and the first conductivelayer is etched into a floating gate using the second polyoxide layer asa mask. A split-gate oxide layer and a second conductive layer areformed on the resulting structure in sequence. A control gate is formedby defining the second conductive layer, and a source region beside thefloating gate is formed in the substrate.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic, cross-sectional view showing a structure of asplit-gate flash memory according to the prior art;

FIG. 2A through FIG. 2I are schematic, cross-sectional views showing aprocess of fabricating a split-gate flash memory according to a firstpreferred embodiment of the invention; and

FIG. 3A through FIG. 3C are schematic, cross-sectional views showing aprocess of fabricating a split-gate flash memory according to a secondpreferred embodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments of the invention disclose methods for fixingthe distance between a drain region and a floating gate in order toensure the channel length of a selective gate. Thus, the invention canensure that the position of the selective gate does not vary with themisalignment of the selective gate.

First Preferred Embodiment of the Invention

FIG. 2A through FIG. 2I are schematic, cross-sectional views showing aprocess of fabricating a split-gate flash memory according to a firstpreferred embodiment of the invention. Referring to FIG. 2A, a isolationstructure (not shown) of a field oxide layer formed by local oxidationor a shallow trench isolation formed by a shallow trench process isformed to define an active area, and a tunneling oxide layer 202 formedby, for example, thermal oxidation is formed to cover a substrate 200.

In FIG. 2A, a first conductive layer 204 having a thickness of about1700-2000 Å and comprising polysilicon formed by, for example, chemicalvapor deposition is formed to cover the tunneling oxide layer 202. Ahard mask 206 having a thickness of about 1500 Å and comprising siliconnitride formed by, for example, chemical vapor deposition is formed tocover the first conductive layer 204.

The hard mask layer 206 is defined by photolithography. For example, aphotoresist layer is formed on the hard mask layer 206. Then, using thefirst conductive layer 204 as an etching stop layer, the hard mask layer206 is defined by the photoresist layer to form a hard mask layer 206 ahaving a drain opening 208 a and a floating gate opening 208 b on thehard mask layer 206 a and to expose the first conductive layer 204 inthe openings as shown in FIG. 2B. According to the first preferredembodiment of the invention, the drain opening 208 a and the floatinggate opening 208 b are in their respective desired positions.

Referring to FIG. 2C, using the hard mask layer 206 a as a mask, thefirst conductive layer 204 exposed by the drain opening 208 a and thefloating gate opening 208 b is oxidized to form a first polyoxide layer210 a and a second polyoxide layer 210 b, respectively. For example, thefirst conductive layer 204 comprising polysilicon is oxidized in an O₂environment to form a polyoxide layer having a thickness of about 1800Å.

Referring to FIG. 2D, a photoresist layer 212 is formed on the secondpolyoxide layer 210 b and covers portions of the hard mask layer 206 b.Using the hard mask layer 206 b and the photoresist layer 212 as a mask,first, an anisotropic etching process with an etching recipe forremoving oxide is performed to remove the first polyoxide layer 210 a toexpose the first conductive layer 204 in the drain opening 208 a, and ananisotropic etching with an etching recipe for removing the firstconductive layer 204 is then performed to remove the first conductivelayer 204 in the drain opening 208 a to expose the substrate 200 in thedrain opening 208 a and to form a first conductive layer 204 a. Theanisotropic etching process is, for example, a plasma etching process.In addition, due to the hard mask 206 and the anisotropic etchingprocess, there may be a remainder 210 a′ of the first polyoxide layer210 a in the drain opening 208 a.

Ions are implanted in the exposed substrate 200 in the drain opening 208a, the photoresist layer 212 is removed, and a drive-in process such asa rapid thermal process for the implanted ions is performed to form adrain 216 as shown in FIG. 2E. Since the drive-in process is performedby a rapid thermal process, an oxide layer 218 is formed on the surfaceof the substrate 200 in the drain region 216. The oxide layer 218 canprevent the drain region 216 from being damaged by a subsequent etchingprocess.

Referring to FIG. 2F, the hard mask layer 206 a is removed by, forexample, wet etching to expose the first conductive layer 204 a coveredby the hard mask layer 206 a. Using the second polyoxide layer 210 b asa mask, an anisotropic etching process such as a plasma etching processis performed to remove the first conductive layer 204 a uncovered by thesecond polyoxide layer 210 b in order to form a floating gate 220. Dueto the remainder 210 a′ of the first polyoxide layer 210 a, there is aremainder 204 a′ of the first conductive layer 204 a beneath theremainder 210 a′ during removal of the first conductive layer 204 a asshown in FIG. 2F. The remainders 210 a′ and 204 a′ are then removed.

Referring to FIG. 2G, a split-gate oxide layer 222 is formed on theresulting structure. A dielectric layer 224 such as a silicon nitridelayer is formed on the split-gate oxide layer 222 and then etched backby, for example, an anisotropic etching process to form dielectricspacers 224 a on sidewalls of the floating gate 220 as shown in FIG. 2H.

Referring to FIG. 2H, a second conductive layer 226 such as apolysilicon layer is formed on the resulting structure by, for example,chemical vapor deposition. Photolithography is performed to define thesecond conductive layer 226 in order to form a selective gate 228 asshown in FIG. 2I. An ion implantation is performed to form a source 230beside the floating gate 220. Since the drain 216 and the floating gate220 are completed before the selective gate 228 being formed, a channellength L₂ of the selective gate 228 is fixed. That is, the channellength L₂ of the selective gate 228 is not affected by the misalignmentof the selective gate 228. Thus, the flash memory can obtain a stablereading current and a stable programming current.

Second Preferred Embodiment of the Invention

FIG. 3A through FIG. 3C are schematic, cross-sectional views showing aprocess of fabricating a split-gate flash memory according to a secondpreferred embodiment of the invention. Description of steps in FIG. 3Athat are the same as the steps in FIG. 2A and FIG. 2B of the firstpreferred embodiment is not repeated here.

Referring to FIG. 3B, a photoresist layer 300 is formed to cover thefloating gate opening 208 b and portions of the hard mask layer 206 a.The first conductive layer 204 exposed by the drain opening 208 a isremoved by, for example, an anisotropic etching process to expose thesubstrate 200. Ions 302 are implanted in the exposed substrate 200 inthe drain opening 208 a.

Referring to FIG. 3C, the photoresist layer 300 is removed to expose thefirst conductive layer 204 a in the floating gate opening 208 b, and adrive-in process for the ions 302 is performed to form a drain 304.Since the drive-in process is performed in an O₂ environment, theexposed substrate 200 in the drain opening 208 a is oxidized into anoxide layer 306, and the exposed first conductive layer 204 a in thefloating gate opening 208 b is oxidized into a polyoxide layer 308. Thesubsequent steps are the same as those in FIGS. 2F-2I; thus, the detailsare not repeated.

According to the invention, since the drain and the floating gate arecompleted before the selective gate is formed, the channel length of theselective gate is fixed. Thus, the channel length of the selective gateis not affected by the misalignment of the selective gate during theselective gate process. As a result, the flash memory can obtain astable reading current and a stable programming current, and thereliability of the flash memory is enhanced.

Other embodiments of the invention will appear to those skilled in theart from consideration of the specification and practice of theinvention disclosed herein. It is intended that the specification andexamples be considered as exemplary only, with a true scope and spiritof the invention being indicated by the following claims.

What is claimed is:
 1. A method for fabricating a split-gate flashmemory, comprising: forming a tunnelling oxide layer, a first conductivelayer, and a hard mask layer on a substrate in sequence; defining thehard mask layer to form a drain opening and a floating gate opening onthe hard mask layer and to expose the first conductive layer; forming afirst polyoxide layer on the exposed first conductive layer of the drainopening and a second polyoxide layer on the exposed first conductivelayer of the floating gate opening; removing the first polyoxide layerand the first conductive layer beneath the first polyoxide layer toexpose the substrate; forming a drain in the exposed substrate; removingthe hard mask layer; forming a floating gate by etching the firstconductive layer while using the second polyoxide layer as a mask;forming a split-gate oxide layer on the substrate and the floating gate;forming a second conductive layer on the split-gate oxide layer;defining the second conductive layer to form a control gate; and forminga source in the substrate beside the floating gate.
 2. The method forfabricating the split-gate flash memory according to claim 1, whereinthe hard mask layer comprises a silicon nitride layer.
 3. The method forfabricating the split-gate flash memory according to claim 1, whereinthe first polyoxide layer and the second polyoxide layer are formed byoxidizing the first conductive layer.
 4. The method for fabricating thesplit-gate flash memory according to claim 1, wherein the step performedto remove the first polyoxide layer and the first conductive layercovered by the first polyoxide layer comprises: forming a photoresistlayer to cover the second polyoxide layer; and performing an anisotropicetching process by using the hard mask layer as a mask to remove thefirst polyoxide layer and the first conductive layer covered by thefirst polyoxide layer.
 5. The method for fabricating the split-gateflash memory according to claim 1, wherein the drain is formed by an ionimplantation, and thereafter, a drive-in process is performed to form anoxide layer on a surface of the substrate in the drain.
 6. The methodfor fabricating the split-gate flash memory according to claim 1,wherein the hard mask is removed by wet etching.
 7. The method forfabricating the split-gate flash memory according to claim 1, wherein inthe step of etching the first conductive layer while using the secondpolyoxide layer as the mask, the etching is an anisotropic etchingprocess.
 8. The method for fabricating the split-gate flash memoryaccording to claim 1, wherein a dielectric spacer on a sidewall of thefloating gate is formed before the second conductive layer being formed.9. The method for fabricating the split-gate flash memory according toclaim 1, wherein the first conductive layer comprises a polysiliconlayer.
 10. The method for fabricating the split-gate flash memoryaccording to claim 1, wherein the second conductive layer comprises apolysilicon layer.
 11. A method for fabricating a split-gate flashmemory, wherein the method applies to a substrate and comprises: forminga tunnelling oxide layer, a first conductive layer, and a hard masklayer the substrate in sequence; defining the hard mask layer to form adrain opening and a floating gate opening on the hard mask layer and toexpose the first conductive layer; removing the first conductive layerin the drain opening to expose the substrate; forming a drain in thesubstrate exposed by the drain opening; forming a polyoxide layer in thefirst conductive layer exposed by the floating gate opening and an oxidelayer on a surface of the substrate; removing the hard mask layer;forming a floating gate by etching the first conductive layer whileusing the second polyoxide layer as a mask; forming a split-gate oxidelayer on the substrate and the floating gate; forming a secondconductive layer on the split-gate oxide layer; defining the secondconductive layer to form a control gate; and forming a source in thesubstrate beside the floating gate.
 12. The method for fabricating thesplit-gate flash memory according to claim 11, wherein the hard masklayer comprises a silicon nitride layer.
 13. The method for fabricatingthe split-gate flash memory according to claim 11, wherein a process forremoving the first conductive layer in the drain opening comprisesforming a photoresist layer to cover the floating gate opening andperforming an anisotropic etching process while using the hard masklayer as a mask to etch the conductive layer and to expose thesubstrate.
 14. The method for fabricating the split-gate flash memoryaccording to claim 11, wherein the drain is formed by implanting ions inthe substrate.
 15. The method for fabricating the split-gate flashmemory according to claim 11, wherein a polyoxide layer is formed on thefirst conductive layer exposed by the floating gate opening, and anoxide layer is formed on a surface of the drain during a drive-inprocess for the drain.
 16. The method for fabricating the split-gateflash memory according to claim 11, wherein the hard mask is removed bywet etching.
 17. The method for fabricating the split-gate flash memoryaccording to claim 11, wherein in the step of etching the firstconductive layer by using the polyoxide layer as the mask, the etchingis an anisotropic etching process.
 18. The method for fabricating thesplit-gate flash memory according to claim 11, wherein a dielectricspacer on a sidewall of the floating gate is formed before the secondconductive layer being formed.
 19. The method for fabricating thesplit-gate flash memory according to claim 11, wherein the firstconductive layer comprises a polysilicon layer.
 20. The method forfabricating the split-gate flash memory according to claim 11, whereinthe second conductive layer comprises a polysilicon layer.